1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device having a MOS transistor with reduced parasitic capacitance.
2. Description of the Related Art
A method of reducing the diffusion layer capacitance between a source/drain high-concentration impurity diffusion region of a MOS transistor and a substrate has been hitherto used to increase the operation speed of a CMOS transistor in a semiconductor device. In order to reduce the diffusion layer capacitance as described above, it is an effective means to reduce the substrate impurity concentration of a channel region, however, the substrate impurity concentration tends to increase more and more as the microstructure of the transistor is more enhanced. In such a condition, a method of restricting doping of impurities into a channel region during the process of forming a channel region of a transistor by a photolithography technique and doping channel ions into only an area where a gate electrode is formed has been hitherto proposed as a method of reducing the diffusion layer capacitance. Further, with respect to recent MOS transistors, in order to enhance the microstructure has been proposed a device structure (so-called pocket structure) in which impurities having the opposite conduction type to that of an LDD-structure or low-concentration impurity layer of a source/drain diffusion layer are doped just below the low-concentration impurity layer to prevent extension of a depletion layer around the source/drain diffusion layer, thereby suppressing a short channel effect. In this structure, existence of the impurities for the pocket also increases the capacitance of the drain diffusion layer, and thus there is used means of doping impurities having the opposite conduction type to that of the drain (source) diffusion layer only in the neighborhood of boundary of the gate-drain (source) diffusion layers.
This conventional technique will be described hereunder with reference to the accompanying drawings. FIGS. 1A to 1D are schematic diagrams showing the process of a conventional method of manufacturing a semiconductor device.
First, as shown in FIG. 1A, a desired well (not shown) and an element isolation region 18 are formed on a semiconductor substrate 1.
Subsequently, as shown in FIG. 1B, a mask 22 is formed by using the photolithography technique, and by using the mask, ion implantation is performed on the area corresponding to a gate electrode formation prearranged portion of the semiconductor substrate 1 (an area of the semiconductor substrate 1 where a gate electrode will be formed), thereby forming a channel region 3.
Subsequently, as shown in FIG. 1C, a gate insulating film 2 is formed, and a gate electrode material is deposited on the gate insulating film 2. A gate electrode 4' is formed at the position corresponding to the channel region 3 by the photolithography technique. The photolithography process of forming the gate electrode 4' needs a margin for positionally matching with the photolithography of the channel region 3 (first mask positioning margin).
Subsequently, as shown in FIG. 1D, a mask 23 is formed by using the photolithography technique, and ion implantation is performed by using the mask 23 and the gate electrode 4' as a mask to form on the semiconductor substrate 1 an LDD-structured low-concentration impurity diffusion layer 12 and an impurity (pocket impurities) layer 13 having the opposite conduction type for suppressing a depletion layer from extending into the inside of the substrate. As in the case of the formation of the gate electrode 4', the photolithography process of forming the mask 23 needs a margin for positionally matching with the photolithography used to form the channel region 3 (second mask positioning margin).
Subsequently, as shown in FIG. 2A, a side wall 14 which is formed of an insulating film is formed on the side surface of the gate electrode 4', and high-concentration impurities are doped into the semiconductor substrate 1 by the ion implantation technique using the gate electrode 4' and the side wall 14 as a mask to form source and drain 15 which correspond to a high-concentration impurity diffusion layer.
Subsequently, as shown in FIG. 2B, an insulating film 20' is formed on the structure formed as described above, and a contact hole 16 is formed in the insulating film 20' to form a wire 17 on the insulating film 20'.
As described above, in the conventional method of the semiconductor device having the MOS transistor, the first and second mask positioning margins are unavoidable on the actual manufacturing process among the process of forming the channel region 3, the process of forming the gate electrode 4' and the process of doping the pocket impurities to form the LDD low-concentration impurity diffusion layer.
In this condition, the overlap area between the source/drain diffusion layer and the channel region is increased due to the positioning margins, and the diffusion layer capacitance between the source/drain diffusion layer and the channel region 3 or the semiconductor substrate 1 is increased. As a result, the operation speed of an electric circuit of the semiconductor device is reduced. The positioning margins as described above are required even when the element is designed more minutely, and thus it is a great obstacle to increase of the operation speed due to miniaturization of the device.